As the semiconductor industry has progressed into nanometer technology process nodes in pursuit of higher device density, higher performance, and lower costs, challenges from both fabrication and design issues have resulted in the development of three-dimensional designs, such as a fin field effect transistor (FinFET). A typical FinFET is fabricated with a thin vertical fin” (or fin structure) extending from a substrate, for example, etched into a silicon layer of the substrate. The channel of the FinFET is formed in this vertical fin. A gate is provided over three sides (e.g., wrapping) the fin. Having a gate on both sides of the channel allows gate control of the channel from both sides. In addition, strained materials in recessed source/drain (S/D) portions of the FinFET utilizing selectively grown silicon germanium (SiGe) may be used to enhance carrier mobility.
However, there are challenges to implement such features and processes in complementary metal-oxide-semiconductor (CMOS) fabrication. For example, it is difficult to achieve a flexible circuit design using a FinFET because the FinFET is formed of a plurality of identical fins for feasible FinFET fabrication.
Accordingly, what are needed are an improved FinFET structure and a method of fabricating the FinFET.